Skip to content

stm32: Change SPI IRQ priority. #17578

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 1 commit into
base: master
Choose a base branch
from

Conversation

yn386
Copy link
Contributor

@yn386 yn386 commented Jun 29, 2025

Summary

On STM32H5/H7, SPI flash cannot use as storage device with DMA.
SPI interruption may not be genearated even if DMA transfer has been done.
This is due to lower priority of SPI interruption than DMA.

This PR changes SPI interrupt priority more higher than DMA's priority.

Testing

Tested:

  • NUCLEO-H563ZI with W25Q32BVSSIG
  • Custom STM32H723VG board with W25Q64JVSIQ

Trade-offs and Alternatives

There is no negative impact because only STM32H5/H7 HAL requires SPI IRQs to be enabled and handled.

On STM32H5/STM32H7, SPI flash cannot use as storage device with DMA.
SPI interruption may not be genearated even if DMA transfer has
been done.
This is due to lower priority of SPI interruption than DMA.

This PR changes SPI interrupt priority more higher than DMA's priority.

Signed-off-by: Yuuki NAGAO <wf.yn386@gmail.com>
Copy link

Code size report:

   bare-arm:    +0 +0.000% 
minimal x86:    +0 +0.000% 
   unix x64:    +0 +0.000% standard
      stm32:    +0 +0.000% PYBV10
     mimxrt:    +0 +0.000% TEENSY40
        rp2:    +0 +0.000% RPI_PICO_W
       samd:    +0 +0.000% ADAFRUIT_ITSYBITSY_M4_EXPRESS
  qemu rv32:    +0 +0.000% VIRT_RV32

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

1 participant